CEO interview: Chips Act boost for RISC-V
Nick Flaherty talks to Calista Redmond, CEO of RISC-V International, on how the European Chips Act is driving the open instruction set architecture forward.
“The recent European summit showed the commercial activity and EU funded activity and there is much stronger path from research to commercialisation because of the EU funding,” said Calista Redmond, CEO of RISC-V International tells eeNews Europe ahead of the North America RISC-V Summit later this month.
“When the community comes together you get a boost, you get the proof points,” she said. “In the past there was stronger reliance on collaborative research in different labs and these now have acceleration to put more confidence into those projects and outcomes.”
“We have organisations coming together for commercialisation such as Quintauris, you have organisations like OpenCHIP, the more stakeholders you bring into the tent the more you have to satisfy and align their requirements.
“But we get that this means RISC-V is the broader global incubator that demonstrates the wider approach to investors and governments. We have 80 workgroups and committees coming together and we have started a certification committee that is coming together, not just for the base ISA but for platforms.”
Global challenges
Formed in Germany, Quintauris aims to accelerate the commercialization of future products based on the architecture, acting as a single source to enable compatible RISC-V based products and provide reference architectures, working with the RISE software consortium.
Backed by Bosch, Infineon, Nordic Semiconductor, NXP Semiconductors, STMicroelectronics and Qualcomm Technologies, the initial focus will be automotive applications, but with an eventual expansion to include mobile and the Internet of Things (IoT).
That flexibility is key for China, which is 17% of the membership of RISC-V International. However there are global trade concerns about RISC-V chips for AI as well as the risk of China developing it own proprietary flavour of RISC-V with its own specific instructions.
“Traditionally a standard might come to bear in hardware from a few major stakeholders and roll out to the world, but we propose a base model with additional specifications so that we satisfy a broader set of stakeholders and our certification initiative will help that,” said Redmond.
“On China, we don’t engage in commercial developments, we provide the composable building blocks of building blocks and RISC-V International is quite well abstracted from the commercial relationships right now,” she said.
Global standard
The key is RISC-V as a global standard, she says.
“Global standards once they are released are free for anyone to leverage or whether you contribute or consumer or both depends on your unique perspective. China is about 17% of our global member so they are a significant stakeholder but this is not a forum for proprietary or differentiated IP. Expert controls are something we pay close attention to and so do members
“Having a standard like RISC-V allows you to avoid vendor lock in and work with the different relationships that you need to take things forwards. It also creates a barrier to creating something that is unique to a geography
“I haven’t seen a divergence from the RISC-V ISA, but any company or country can add their own extensions. There is a space for proprietary extensions.”
Security
Security is also a key factor in RISC-V chip designs.
“Security is absolutely paramount, and we address security proactively. One vulnerability was found to be implementation unique and whenever there is a heightened concern we dive into it.”
This was the recent vulnerability called GhostWrite that was found by a team at the Helmholtz Centre for Information Security in Germany. This impacts the XuanTie C910 and C920 RISC-V CPUs designed by T-Head in China that are used in a range of single board computers.
The vulnerability in the RISC-V vector extensions allows unprivileged attackers, even those with limited access, to read and write any part of the computer’s memory and to control peripheral devices such as network cards. GhostWrite renders the CPU’s security features ineffective and cannot be fixed without disabling around half of the CPU’s functionality.
The bug uses faulty instructions in its vector extension that work directly with physical memory instead of virtual memory, bypassing the process isolation normally enforced by the operating system and hardware. This bug is embedded in the hardware, meaning it cannot be fixed with software updates.
Software
Software is a key area for focus, says Redmond.
“With the growth we are coming into challenges where we want to accelerate the ecosystem. Those are the areas we are focussing on first, to port workloads, software stacks
“Now the business case is there, the [chip] volumes are coming on and that is instrumental for the software,” she said. “Quintauris is a matter of timing and market maturity. We are already seeing in embedded that RISC-V is a leader there, grabbing more market share and we anticipate that growing into mobile and datacentre chips, there is strategic investment in AI and machine learning to add differentiation. Wherever there is greenfield that’s where we are growing.”
“Continuing to refine and tune that ecosystem is essential. It’s when suppliers and customers come to them to say they want RISC-V,” she said.
This is highlighted by the increasing number of startups developing RISC-V chips, from Akeana and Red Semiconductor to two teams of designers who previously worked for Intel.
“I think that the startups we have seen from SiFive to Quintauris and OpenCHIP is they have the ability to grab top talent and the talent is open to joining those organisations, so when high calibre folks are making career choices they need to be reassured there is a strength there.
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