D-Wave announces initiative for advanced cryogenic packaging
D-Wave Quantum has announced a new strategic development initiative focused on advanced cryogenic packaging. Designed to advance and scale both gate model and annealing quantum processor development, the new initiative builds on D-Wave’s technology leadership in superconducting cryogenic packaging, expanding its multichip packaging capabilities, equipment, and processes. By bolstering manufacturing with state-of-the-art technology, D-Wave aims to accelerate its cross-platform technology development while maintaining and expanding fundamental components of its supply chain.
As part of this initiative, D-Wave is leveraging deep expertise and processes at the NASA Jet Propulsion Laboratory (JPL), a research and development lab federally funded by NASA and managed by Caltech. End-to-end superconducting interconnect between chips has been demonstrated using the JPL superconducting bump-bond process. D-Wave expects the work with JPOL will serve as an important foundation for scaling both its annealing architectures and its fluxonium-based gate-model architectures. D-Wave believes that superconducting bump bonds will be key to the scalable control of fluxonium and interconnectivity in multichip quantum processor architectures.
D-Wave is also acquiring equipment and developing processes to increase circuit densities in its pioneering superconducting printed-circuit-board (PCB) manufacturing, required for both scaling to larger processors and supporting analogue-digital quantum computing technology.
“Scaling both annealing and gate-model quantum computers requires high-performance packaging,” said Dr. Trevor Lanting, chief development officer at D-Wave. “We believe this strategic initiative will allow us to further extend our leadership position in quantum systems technology development and support our exciting and aggressive product roadmap on the path to 100,000 qubits.”
Packaging quantum processors involves unique and demanding requirements, including: compatibility with ultra-low temperature operation, extremely low magnetic fields, and fully superconducting interconnects with no interruptions in superconductivity from on-chip circuitry through to external control wiring. D-Wave’s differentiated solution encompasses cryogenic-compatible mechanical and electromagnetic design, regularly achieves lower qubit temperatures than most in the industry, and supports coherence times that meet the requirements for error-corrected gate-model quantum computing technology.
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