The transition toward software-defined vehicles is pushing automotive electronics toward more centralized computing platforms. Multi-domain electronic control units are increasingly expected to consolidate workloads such as ADAS and vehicle control within a single processing environment, placing growing demands on automotive SoC architectures that can manage multiple domains within a unified processing platform.
Renesas advances automotive SoC technologies for multi-domain ECUs in SDV architectures
Technology News
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By
Alina Neacsu
For eeNews Europe readers, this development reflects the growing complexity of automotive semiconductor design. It also highlights how chip architecture, power management and AI acceleration are becoming critical elements in next-generation vehicle computing platforms.
Chiplet architecture aims to support functional safety
Renesas has presented three system-on-chip technologies designed for automotive multi-domain ECUs, targeting the evolving requirements of software-defined vehicles (SDVs). The company showcased the technologies at the International Solid-State Circuits Conference (ISSCC) 2026.
One key area of development is a chiplet-based architecture intended to support functional safety at the highest automotive level. Multi-domain ECUs increasingly rely on chiplet configurations to scale performance, but ensuring safe interaction between processing domains can be challenging.
Renesas said it has developed a proprietary architecture that enables ASIL D compliance even when multiple chiplets are used. The design combines the UCIe die-to-die interface with a mechanism that assigns RegionIDs to hardware resources, helping prevent interference between applications running concurrently. This approach is intended to provide Freedom from Interference, an important requirement in safety-critical automotive systems.
Such architectures may become increasingly relevant as central vehicle computers integrate more functions across domains such as perception, control and connectivity.
AI processing and power management improvements
Another focus of the work is improving AI processing capability while maintaining automotive-grade reliability. The company described a 3 nm automotive SoC design that supports larger neural processing units used for AI workloads.
To address increasing clock latency in larger NPU architectures, Renesas redesigned the clock generation structure by introducing smaller clock generators at the sub-module level. This approach potentially reduces latency while maintaining timing accuracy for complex AI accelerators.
At the same time, the design integrates test and clock synchronization mechanisms intended to support zero-defect quality targets typical in automotive electronics.
Power management is also addressed through a new power-gating scheme using more than 90 power domains. This allows fine-grained control over energy consumption, from milliwatts to tens of watts, depending on workload conditions. The company said the design reduces IR drops by about 13% compared with conventional approaches.
Additional safety features include dual-core lockstep operation and voltage monitoring designed to maintain reliable operation under varying conditions.
Renesas said these technologies are being applied in its R-Car X5H processor for automotive multi-domain ECUs, which targets centralized vehicle computing platforms in future SDV architectures.
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