Siemens EDA buys chip timing tool Excellicon
Siemens Digital Industries Software is to buy US timing tool startup Excellicon.
The deal enables Siemens to deliver an innovative approach to both implementation and verification flows -enabling System-on-a-Chip (SoC) designers to improve power, performance and area (PPA), accelerate design closure through the timing closure.
This comes as Siemens highlights that first silicon success is declining, down from 24% in 2022 and 32% in 2020 to just 14% in 2024. Timing closure is a key challenge for more complex chip designs.
“Effective timing constraints management is crucial for the overall success of semiconductor system-on-chip designs,” said Mike Ellow, CEO of Siemens EDA. “Excellicon’s constraint verification and management solution complements Siemens’ existing EDA offerings and expands our portfolio into key market segments in flows with the Questa, Tessent, Aprisa and PowerPro products.”
Excellicon’s tools cover timing constraints authoring, compiling, verification, formal validation and management using a multi-mode approach that bridges early design concepts with their physical implementation. This gives insights into partitioning schemes for optimal floorplans and timing. The tools are used by Mediatek, Renesas Electronics, Socionext and LG Electronics and are included in the Samsung FOundry tool flow.
These will be integrated into both the implementation and verification flows.
“We are delighted to join Siemens and bring our knowledge and expertise in timing constraints management to the wider Siemens EDA community,” said Himanshu Bhatnagar, CEO, Excellicon. “Together, we’ll be able to provide better process coverage and enable our customers to deliver robust innovation to market more quickly and overcome the ever-growing complexity challenges facing the IC industry.”
Siemens says the terms of the deal, which is expected to close in a few weeks, were not disclosed.
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