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RISC-V Page 7

RISC-V Page 7
Codasip, Siemens to deliver trace for custom processors
Codasip, Siemens to deliver trace for custom processors
Technology News |
Tessent™ Enhanced Trace Encoder enables significant productivity gains even in the most complex heterogeneous and custom designs.
First 22nm FGPA with hardened RISC-V cores
First 22nm FGPA with hardened RISC-V cores
New Products |
Gowin Semiconductor has hardened a RISC-V core and peripherals and embedded them into its latest 22nm FPGA. The GW5AST-138 FPGA…
PolarFire FPGAs verified for single-chip cryptography design flow
PolarFire FPGAs verified for single-chip cryptography design flow
Business news |
Security strength of the FPGAs has been confirmed by the UK National Cyber Security Centre when used with the Single-Chip…
Fraunhofer IPMS contributes to RISC-V research, offers IP
Fraunhofer IPMS contributes to RISC-V research, offers IP
Technology News |
A RISC-V processor IP, the EMSA5 is a 32-bit processor with a five-stage pipeline for embedded and automotive systems.

Hot Chips 2023 – SiFive P870 RISC-V processor
Hot Chips 2023 – SiFive P870 RISC-V processor
News |
At Hot Chips SiFive is giving a tour on the new P870 processor – an STH report and slides   Over the year SiFive has been pushing out the…
Think and Tinker your own IoT solutions
Think and Tinker your own IoT solutions
New Products |
Think and tinker your own IoT solutions with the Tinker V board from Asus IOT This versatile single-board computer (SBC) is powered by a 64-bit RISC-V-based processor, which supports both…
German AI RISC-V joint venture poses challenge to ARM
German AI RISC-V joint venture poses challenge to ARM
Business news |
Major semiconductor companies in Europe are setting up a German-based company to drive the adoption of RISC-V hardware and AI architectures. The venture brings together Robert Bosch, Infineon Technologies, Nordic…
Fully customisable 4-way RISC-V core for big data
Fully customisable 4-way RISC-V core for big data
Technology News |
Semidynamics in Spain has developed a customisable 4-way RISC-V 64bit core for data centre chips. The Atrevido 423 RISC-V core has a wide 4-way pipeline for decoding and retiring twice…
BeagleV®-Ahead single board computer available from Farnell
BeagleV®-Ahead single board computer available from Farnell
Business news |
The newly launched BeagleV®-Ahead is the first professional, mass production RISC-V SBC board by Beagleboard.org®.
Imperas details verification of automotive AI RISC-V vector processor IP
Imperas details verification of automotive AI RISC-V vector processor IP
Technology News |
Imperas Software in the UK and Cadence Design Systems have detailed the verificaiton flow for NSITEXE developing an automotive AI RISC-V processor core. The two worked on a comprehensive verification…
Bluespec Launches New MCUX RISC-V Processor
Bluespec Launches New MCUX RISC-V Processor
New Products |
The new processor enables Developers to Implement Custom Instructions and Add Accelerators Bluespec Inc. announced its new MCUX RISC-V processor that makes it easy for developers to implement custom instructions…
Tailor Made RISC-V Performance – eeNews interview with Roger Espasa/Semidynamics
Tailor Made RISC-V Performance – eeNews interview with Roger Espasa/Semidynamics
Business news |
The RISC-V Instruction Set Architecture is perfectly suitable for fine tuning the performance depending on the application. In this interview Roger Espasa, CEO and Founder at Semidynamics Technology Services explains…
An Analog Guy in a Digital World – Interview with Chris Morrison
An Analog Guy in a Digital World – Interview with Chris Morrison
Interviews |
We are living in a digital world, but the real world is analog. You need sensors and Analog to Digital converters to interface between these two worlds. ‘For a lot…
‘The future is in custom compute’ – eeNews interview with Zdeněk Přikryl, Codasip
‘The future is in custom compute’ – eeNews interview with Zdeněk Přikryl, Codasip
Interviews |
At the RISC-V summit in Barcelona, eeNews is meeting up with Zdeněk Přikryl, CTO at Codasip. We discuss the ‘custom compute’ options and Codasip Studio. This tool enables you to…
RISC-V gathers pace in Europe
RISC-V gathers pace in Europe
Feature articles |
The RISC-V Summit Europe brought together developers, architects, technical decision and policy makers from across European RISC-V ecosystem for the first time in the region this week. Attendees from academia,…
RTL verification for Caliptra’s RISC-V VeeR core
RTL verification for Caliptra’s RISC-V VeeR core
Technology News |
Antmicro and Google have detailed an open source approach to verification of RISC-V cores that fits with modern software development processes. The Caliptra project uses the VeeR (Very Efficient &…
SAFERTOS ported to Microchip’s RISC-V soft core
SAFERTOS ported to Microchip’s RISC-V soft core
News |
Wittenstein High Integrity Systems (WHIS) has ported its safety critical real-time operating system (RTOS) to the MiV_RV32 RISC-V soft CPU IP from Microchip and joined the Mi-V Ecosystem. The MiV_RV32 RISC-V…
Imagination, GHS team for RTOS and tools on RISC-V CPUs
Imagination, GHS team for RTOS and tools on RISC-V CPUs
Business news |
Green Hills Software has ported its µ-velOSity safety- and security-certified real-time operating system (RTOS) to the real time RISC-V cores developed by Imagination Technologies, with plans to support Imagination’s Catapult…
Startup plans customizable RISC-V edge AI speech processor
Startup plans customizable RISC-V edge AI speech processor
Technology News |
AONDevices has developed an efficient edge AI denoising technology for applications that require minimal power and latency running on its forthcoming accelerator IP and hardware as well as third party…
Computing at the Ultimate Edge – Space
Computing at the Ultimate Edge – Space
Interviews |
eeNews Europe is meeting up with Gerard Rauwerda, Business Developer with Technolution. We discuss the RISC-V developments over the years and the role Technolution played, but also what specific requirements…
Interview with Calista Redmond – RISC-V summit Barcelona
Interview with Calista Redmond – RISC-V summit Barcelona
Interviews |
At the RISC-V summit in Barcelona eeNews is meeting up with Calista Redmond. She is the CEO of RISC-V International. In our conversation we are talking about what Europe has…
Ashling SDK supports German SIM-V RISC-V Instruction Set Simulator
Ashling SDK supports German SIM-V RISC-V Instruction Set Simulator
Business news |
Ashling’s RiscFree software development kit (SDK) now provides target debug support for the SIM-V RISC-V Instruction Set Simulator developed by MachineWare in Germany. MachineWare’s SIM-V is a RISC-V simulator enables…
The RISC-V Report – interviewing the key players (2017-2023)
The RISC-V Report – interviewing the key players (2017-2023)
Market news |
Take time for the The RISC-V Summit in Barcelona and connect the dots of this Open Instruction Set Architecture In 2017 we had the opportunity to interview Krste Asanovic about…
AI/ML flow for PolarFire RISC-V FPGAs in edge designs
AI/ML flow for PolarFire RISC-V FPGAs in edge designs
New Products |
Microchip Technology has launched a mid-range industrial edge stack for its PolarFire RISC-V FPGAs with an AI/ML development flow. PolarFire includes the only RISC-V SoC FPGA shipping in volume production,…
Dolphin Design picks Imperas for processor functional verification
Dolphin Design picks Imperas for processor functional verification
Business news |
ImperasDV enables ‘step-compare’ advanced functional verification including asynchronous events, plus verification IP reusability with RVVI.
Complete RISC-V analog IP subsystem targets IoT
Complete RISC-V analog IP subsystem targets IoT
New Products |
Initial subsystem includes all the analog IP required for a typical battery powered RISC-V based IoT system, accelerating time to market.
Agile Analog launches first complete RISC-V analog IP subsystem
Agile Analog launches first complete RISC-V analog IP subsystem
New Products |
Agile Analog has brought together its customisable IP blocks to create the first complete analog IP subsystem for battery-powered RISC-V chips. The initial subsystem includes all the analog IP required…
RISE to boost development of open source RISC-V software
RISE to boost development of open source RISC-V software
Business news |
Chip designers are at the heart of a new project to boost the development of open source software for the RISC-V instruction set. The RISC-V Software Ecosystem (RISE) Project is…


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