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RISC-V Page 8

RISC-V Page 8
Fully customisable vector unit complements 64-bit RISC-V cores
Fully customisable vector unit complements 64-bit RISC-V cores
New Products |
RISC-V Vector Specification 1.0 compliant, the vector unit delivers up to 2048b of computation per cycle for unprecedented data handling…
Semidynamics launches configurable RISC-V vector unit
Semidynamics launches configurable RISC-V vector unit
Technology News |
Semidynamics in Spain has developed a highly configurable out of order vector unit with a new architecture to boost performance…
MIPS taps Siemens FPGA for RISC-V CPU roll out
MIPS taps Siemens FPGA for RISC-V CPU roll out
Business news |
MIPS is using an FPGA platform from Siemens Digital Industries Software to accelerate software development for its eVocore P8700 RISC-V…
FIVEberry RISC-V board for fast prototyping
FIVEberry RISC-V board for fast prototyping
New Products |
Aries Embedded in Germany has launched a fast prototyping RISC-V board based on the RZ/Five microprocessor from Renesas Electronics. The…

SiFive donates WorldGuard security to RISC-V International
SiFive donates WorldGuard security to RISC-V International
Business news |
SiFive is to donate its WorldGuard security technology to RISC-V international in a bid to create a consistent security platform across the RISC-V community. The fragmented security eco-system is seen…
Axelera AI increases its Series A funding round to $50m for RISC-V edge AI chip
Axelera AI increases its Series A funding round to $50m for RISC-V edge AI chip
Business news |
Dutch startup Axelera AI has raised $50m for its in-memory computing, RISC-V-based edge AI technology and set up a Silicon Valley office. CDP Venture Capital, Verve Ventures and Fractionelera have…
Meta details its first custom RISC-V AI silicon
Meta details its first custom RISC-V AI silicon
Feature articles |
Meta has revealed details of the first chip it designed in house using RISC-V to run AI frameworks for its Facebook and Instagram services. The company found that GPUs were…
Ubuntu on VisionFive 2 RISC-V single board computer
Ubuntu on VisionFive 2 RISC-V single board computer
New Products |
Canonical published the optimised Ubuntu release for StarFive’s VisionFive 2, the world’s first high-performance RISC-V single board computer (SBC) with an integrated GPU VisionFive 2 is the world’s first…
Codasip, Codeplay to combine RISC-V and SYCL for open AI accelerator chips
Codasip, Codeplay to combine RISC-V and SYCL for open AI accelerator chips
Technology News |
Eight European organisations including Codasip and Codeplay are aiming to combine the RISC-V and SYCL standards for AI acceleration. The SYCLOPS (Scaling extreme analYtics with Cross-architecture acceleration based on Open…
Learn RISC-V with the ‘Earth and Grass Operating System’
Learn RISC-V with the ‘Earth and Grass Operating System’
Technology News |
This 2000 lines of code OS Egos will bring you to the hearth of the RISC-V architecture Yunhao Zhang from the Cornell Uni developed a operating system in only 2000…
Compiler test update boosts Andes RISC-V in automotive
Compiler test update boosts Andes RISC-V in automotive
Business news |
Andes Technology has upgraded its version of the SuperTest Compiler Test and Validation Suite developed and supplied by Solid Sands in the Netherlands to support its growth in automotive chip…
RISCs ‘not-in-Space’ (with statement from the Pulp Platform)
RISCs ‘not-in-Space’ (with statement from the Pulp Platform)
News |
The 432-Core Risc-V based Occamy processor board is ready to launch – with updated link! The ETH in Zurich, together with the Alma Mater Studiorum Universita di Bologna presented the…
RISC-V ratifies compressed instruction extensions
RISC-V ratifies compressed instruction extensions
Technology News |
RISC-V has ratified its extensions for code compression to reduce the memory requirements when using the open instruction set architecture. This is particularly important for microcontrollers that have limited memory…
General purpose SDK to accelerate parallelized HPC workloads
General purpose SDK to accelerate parallelized HPC workloads
New Products |
The ET-SoC-1 AI inference chip with over 1000 64-bit RISC cores can now be programmed directly using standard C or C++ to accelerate non-AI workloads.
Menta, Codasip join RISC-V 3D neuromorphic AI project
Menta, Codasip join RISC-V 3D neuromorphic AI project
Technology News |
The research wing of European RISC-V processor core developer Codasip and French embedded FPGA firm Menta have joined a project to build a 3D neuromorphic AI chip. The €10m NimbleAI…
Esperanto runs generative-AI on RISC-V
Esperanto runs generative-AI on RISC-V
Technology News |
Esperanto Technologies Inc. (Mountain View, Calif.) has announced it has ported a range of generative AI models to its RISC-V hardware. Initial work includes running a range of large language…
New CTO at Tasking looks to Rust and RISC-V
New CTO at Tasking looks to Rust and RISC-V
Business news |
Christoph Herzog has taken over the new role of Chief Technical Officer (CTO) at development tool vendor Tasking in Germany. The CTO role was created to implement and drive the…
EdgeQ closes investment for 5G+AI Base Station-on-a-Chip
EdgeQ closes investment for 5G+AI Base Station-on-a-Chip
Business news |
Massively integrated 4G+5G+AI chip uniquely leverages both RISC-V and ARM architectures to enable simple, scalable, and affordable Open RAN networks.
Secure RISC-V accelerator startup VyperCore raises £4 million
Secure RISC-V accelerator startup VyperCore raises £4 million
Technology News |
VyperCore Ltd. (Bristol, England), a startup with plans to develop novel processor technology, has raised £4 million (about US$5 million) in seed funding. The company was founded by Ed Nutting,…
Process agnostic fully customisable RISC-V IP cores
Process agnostic fully customisable RISC-V IP cores
Technology News |
Customisable RISC-V IP cores ideal for handling large amounts of data and highly sparse data with long latencies.
Spanish startup performs RISC-V open core surgery
Spanish startup performs RISC-V open core surgery
Interviews |
Spanish startup SemiDynamics has developed fully configurable 64bit RISC-V processor IP for high performance chip designs in AI, Machine Learning (ML) and High-Performance Computing (HPC). The customisable cores are process…
Nordic combines ARM M33 and RISC-V cores in fourth generation Bluetooth chip
Nordic combines ARM M33 and RISC-V cores in fourth generation Bluetooth chip
New Products |
Nordic Semiconductor has launched its fourth generation multicore low power Bluetooth chip, combining multiple ARM and RISC-V cores on a silicon on insulator process technology. The nRF54H20 uses multiple ARM…
Renesas launches RISC-V voice recognition chip
Renesas launches RISC-V voice recognition chip
Technology News |
Renesas Electronics has developed its first RISC-V microcontroller designed for voice recognition interfaces systems using IP from Andes. The R9A06G150 32bit application specific processor (ASSP) provides a complete, cost-effective, production-ready voice-control…
Baidu backs RISC-V startup for Chinese datacentre chip
Baidu backs RISC-V startup for Chinese datacentre chip
Business news |
Chinese cloud giant Baidu has invested in StarFive to develop a high performance computing (HPC) chip based on the RISC-V instruction set. Competitors Alibaba and Tencent have both shown RISC-V…
RISC-V boost from LLVM 16 compiler
RISC-V boost from LLVM 16 compiler
Technology News |
Development with RISC-V chips has seen a significant boost with the latest release of the LLVM open source compiler that underpins many industry tools. For the first time the architecture…
CEO Interview: Calista Redmond of RISC-V International at Embedded World 2023
CEO Interview: Calista Redmond of RISC-V International at Embedded World 2023
Interviews |
Calista Redmond, CEO of RISC-V International talks to Nick Flaherty at Embedded World (EW2023) about the open instruction set architecture breaking out of embedded. “We are at maturity point and…
Codasip, IAR show dual-core lockstep for RISC-V safety designs
Codasip, IAR show dual-core lockstep for RISC-V safety designs
Technology News |
Codasip and IAR have developed a dual-core RISC-V processor that operates in lockstep, opening up a route to ISO 26262-qualified embedded applications based on the versatile Codasip L31 core. Other groups, particularly Fraunhofer,,…
Imperas in RISC-V three way deal
Imperas in RISC-V three way deal
News |
Imperas Software has signed a three-way collaboration with MIPS and Ashling across all aspects of RISC-V software development. The three will use the Imperas reference models for the MIPS eVocore…


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