The shifting sands of MCUs
The rise of AI is shifting the requirements for simple microcontrollers (MCUs). Code produced with AI and the growing demand for AI inference, coupled with the need to have secure systems with coming standards such as Cyber Resilience Act (CRA), is changing the way microcontrollers are used in system designs. Moving to more aggressive process technologies at 22nm is allowing new memory technology such as MRAM to be used with higher performance at lower cost, boosting the entry of new architectures for MCUs into the market, all on show this week at the Embedded World exhibition in Nuremberg, Germany.
Memory safety
SCI Semiconductor is showing first silicon of its ICENI secure 32bit microcontroller, the first commercial device to use the CHERI (Capability Hardware Enhanced RISC Instruction) secure memory architecture.
The ICENI device combines the RISC-V RV32E instruction set with the CHERI hardware architecture so that a simple recompile allows legacy code and AI-generated code to be much more secure by taking advantage of security features embedded in the hardware.
“There seems to be a massive gap between the exploits and vulnerabilities and understanding the root of the problem,” Haydn Povey, CEO of SCI Semiconductor, tells eeNews Europe.
He aims to take advantage of the boom in AI coding, ensuring that AI-generated code runs safely on the microcontroller.
“The cost of development on CHERI will be cheaper as we purposely embrace code reuse, tools such as CodeForge and AI generated code. Run it, it’s safe, you don’t have to be using Linux for thread isolation as its done in the hardware and the energy drops,” he said.
This memory safety is achieved with the CHERI hardware-enforced capability model developed with Microsoft and the University of Cambridge. This model replaces traditional pointers with unforgeable, bounded capabilities that include metadata specifying the precise memory regions and permissions they grant. By ensuring that software components can access only the memory explicitly delegated to them, ICENI enforces strong spatial memory safety by construction, preventing entire classes of exploits before they can occur.
“In the first instance to use memory safety to remove the vulnerabilities the effort is low, it is a recompile to make use of the ISA extensions,” he said. “But that recompile is as lightweight as it can possibly be with C, C++ or Rust so you should not have to make any changes to the code. In embedded development everyone recompiles when they make a small change so there is a fairly natural adoption. That removes 70% of critical vulnerabilities. The next thing to move to a higher resilience layer with compartmentalisation via instrumentation of the call stacks. This has less than 2% code impact.”
This compartmentalisation of the code limits the ‘blast radius’ of any attack that does get through. This approach contains faults or compromises without the complexity and performance penalties of protection model used by legacy microcontrollers and avoids the need to go to larger, more power hungry microprocessors with memory management units.
The ICENI microcontroller is built on the low power 22FDX silicon on insulator process at GlobalFoundries in Dresden. “This means we are European sovereign which is very important to a number of our initial companies and it does allow us to produce in the US. It makes a lot of sense,” said Povey.
Silicon Labs
At the same time Silicon Labs is planning its Series 3 range of MCUs ahead of its acquisition by Texas Instruments.
“The big difference with the Series 3 22nm platform is really the digital content, with customer software running alongside the wireless stack,” Daniel Cooley, CTO of Silicon Labs tells eeNews Europe.
“That means higher value applications that need real time operating systems and off chip flash for execute in place (XIP) as customers have been held up with cache misses.”
“As we have engaged with customers on smart caching they find its not that big of a deal for XIP, and there is not a big performance hit for moving off chip. This means they can have a much more scalable software.”
“We have software profiles to run through and optimise caches for embedded applications and an authenticated XIP interface, which is a big deal with Internet connectivity
“On the AI side inference is big business. If there is any kind of sensor feed they want machine learning and we have multiple accelerators that we will be using, and having split out what is proprietary and what is standards-based,” he said. “I see ARM pushing a roadmap that looks attractive with the U55 and U85 AI accelerators. How we package things up we haven’t announced yet.”
“One thing we are seeing is that 2018 to 2022 microcontrollers had proprietary accelerators, but since 2024 there has been a shift to licensed accelerators.”
Security will also be key for MCUs. “The CRA is coming next and that’s the real challenge. It’s going to be big,” said Cooley.
Similarly the target for SCI for the ICENI microcontroller is critical infrastructure, including the digitalisation of the electricity grid.
“The critical areas we see first are aerospace and defence but in the more mainstream we do see people who deliver into critical infrastructure and they are the ones really leading this as it’s a shorter time to market,” said Povey. “If you look at something like the smart grid the treasury has already signed funding for £18bn and the criticism is its moving too slowly. But what we build into the smart grid needs to be resilient and flexible for 50 years so there is a very big push to have things that are connected.”
The software ecosystem is key for the adoption, and SCI has worked with the AWS FreeRTOS stack to move all the critical aspects into separate compartments so that when a flaw is discovered the blast radius of the attack vector is reduced. “We automatically mitigated five new CVEs that emerged after we did the work,” said Povey.
He points to the CHERI Alliance with partners developing software for the microcontroller such as a real time operating system (RTOS) and the CRA that comes into force this year.
“We have co-developed the CHERI RTOS so out of the box we have a full blown RTOS that meets all the software and application requirements of CRA, as we can lock down flaws so they don’t become issues, it’s a run flat tyre for the software, and that meets the CRA,” he said. “It was started at Microsoft and was open sourced with us and Google. When we look across commercial RTOSes they have been built for safety or determinism rather than security, so the opportunity was there to create the RTOS from scratch. It gives us a tiny code base of 350 instructions that is formally proven by the University of Oxford along with the ISA and kernel requirements and then you layer security on top of that.”
“The first implementations are for AA or AAA batteries as we had to move fast on the development so there isn’t power islanding, so we are not doing coin cells,” he said. “We are typically 30% more expensive than other MCUs but that price will come down with volume, but this is not a 2x or 10x price differential.”
Independence
Nordic Semiconductor in Norway has the same challenge as Silicon Labs with remaining independent as a microcontroller supplier. In the meantime it has bought a remote fault detection software developer, Memfault, to extend its software ecosystem.
It has now launched two smaller Bluetooth wireless MCUs for more cost effective, high volume applications such as wearables. The nRF54LS05A and nRF54LS05B offer developers the key features of the nRF54L Series – robust Bluetooth LE connectivity, low-power consumption, and easy-to-use software – while optimizing for the development of simple, cost-efficient Bluetooth LE end-products. Nordic’s Bluetooth LE stack serves the reference for the streamlined development of entry-level, simple applications such as sensors, tags, beacons, remotes, and PC peripherals.
“With both the nRF54LS05A and nRF54LS05B, we want to give developers an easy, confident starting point,” says Øyvind Strøm, vice president for short-range wireless at Nordic Semiconductor. “Offering the fundamental features of our standard Bluetooth LE SoCs in combination with our software ecosystem offering ease of use, both SoCs will help level the playing field for those building lean, cost-sensitive applications”.
The MCUs combine a 128 MHz ARM Cortex M33 with low-leakage RAM for efficient, responsive processing in compact, ultra-low-power wireless designs. They include Nordic’s fourth-generation multiprotocol Bluetooth LE radio, baseline security, and pin-to-pin compatibility with selected SoCs in the series for easy scalability.
While both SoCs offer the same level of Non-Volatile Memory (NVM) at 0.5 MB, the nRF54LS05A offers a modest increase to 64 KB of RAM, and 96 KB in the nRF54LS05B.
The series supports several wireless protocols, including Bluetooth LE, Matter, Thread, Zigbee, and 2.4 GHz modes and is ready for evaluation and development. Production is expected to start in Q3 2026.
AI accelerators
At the same time Texas Instruments has launched MCUs with its TinyEngine neural processing unit (NPU) hardware accelerator. The MSPM0G5187 and AM13Ex MCUs integrate the TinyEngine NPU to reduce latency and improve energy efficiency when processing at the edge.
The MSPM0G5187 is based around the ARM Cortex-M0+ MSPM0 MCU and represents a fundamental shift for embedded designers at under $1 in 1000 unit volumes, says TI. The on-chip TinyEngine lowers latency by up to 90 times per AI inference and reduces energy utilization by more than 120 times per AI inference.
The MCUs are supported by a new version of the CCStudio integrated development environment (IDE) that uses generative AI features allow engineers to use simple language to accelerate code development, system configuration and debugging through industry-standard agents and models paired with TI data.
“TI invented the digital signal processor almost 50 years ago, laying the groundwork for today’s edge AI processing,” said Amichai Ron, senior vice president, Embedded Processing and DLP Products at TI. “Now TI is leading the next phase of innovation by integrating the TinyEngine NPU across our entire microcontroller portfolio, including general-purpose and high-performance, real-time MCUs. By enabling AI across our software, tools, devices and ecosystem, we are making edge AI accessible and easy to use for every customer and every application.”
“While much of the world has been focused on AI acceleration and NPUs in bigger SoCs, it turns out some of the more interesting and far-reaching applications of AI can be enabled inside smaller chips like microcontrollers,” said Bob O’Donnell, President and Chief Analyst at TECHnalysis Research. “Edge-based applications of AI acceleration can make consumer devices more intelligent and industrial devices more efficient. Plus, if you can combine these chips with software development tools that themselves leverage AI to help build AI features, you bring the power of AI acceleration to a significantly wider audience of engineers and device designers.”
Wearable AI
Low power AI microcontroller startup Ambient Scientific has teamed up with Indian VR company Dimension NXG as it expands into wearable sensors. Dimension has developed a women’s safety wearable called MAI with always-on AI and two-week battery life by using Ambient’s GPX-10 AI microcontroller.
The MAI wearable uses the GPX10 AI microcontroller from Ambient Semiconductor
The GPX-10 MCUs use in-memory processing with both digital and analog components for the 10 MAC blocks to achieve low power, along with an ARM M4 core.
MAI is a women-first health companion with a built-in safety layer. It tracks everyday vitals like heart rate and SpO₂ and can support blood-pressure insights based on sensing configuration, turning daily signals into actionable health awareness.
“The band is to be used for women’s health and safety with biosignal tracking with on device AI features including fall detection. In the SE Asian market, safety is a prevalent issue, being able to detect assaults, trigger alerts, completely on the device in real time,” GP Singh, CEO of Ambient tells eeNews Europe. “It will also have algorithms to detect female medical conditions on-device to make sure the medical data remains on the device, with a battery life of two weeks. The GPX10 acts as the main controller with an ARM M4 with 10 of our cores, controlling the communications chip.”
The MAI wearable will enter field trials next week with thousands of devices deployed to pre-order customers and trial participants across India. Dimension NXG then plans to scale to over 10,000 units by the end of the year as the product attains further medical-grade certifications.
Lower cost microcontrollers
STMicroelectronics is pushing its MCUs into more areas by driving costs down to $0.64 in high volume. The latest generation STM32C5 entry-level ARM M33 microcontrollers is aimed at applications such as smart thermostats, electronic door locks, industrial smart sensors, robotic actuators, wearable electronics, and computer peripherals.
A new design on a 40nm process provides higher performance at 144MHz for improved sensing and smoother control as well as integrating more safety and security features. These include protection against side channel attacks and on-chip encryption.
Drivers have been optimised for the family to keep the memory size down, with variants providing up to 1024 Kbytes of flash and 256 Kbytes of SRAM, along with Ethernet, OctoSPI, and FDCAN interfaces.
The devices are as small as 3mm x 3mm in UFQFPN20 packages to 20mm x 20mm in LQFP144:
The STM32C5 family from ST Microelectronics
“The STM32C5 elevates the precision, speed and reliability of competitively priced MCUs to realize the potential in these opportunities. It builds on two decades of STM32 heritage and is part of our ambition to deliver the broadest, most scalable and secure portfolio from entry-level devices to advanced MCUs that redefine the application reach of embedded systems,” said Patrick Aidoune, Group Vice President and General Purpose and Automotive Microcontrollers Division General Manager at STMicroelectronics.
ST’s Nucleo evaluation boards, and a display extension board from Riverdi with TouchGFX development software for building entry-level graphical user interfaces, are ready to assist development.
Robotics
GlobalFoundries acquiring the MIPS range of microcontrollers and microprocessors was a major shift for the market.
Now a collaboration with Inova Semiconductors in Germany aims to deliver a reference platform for advanced humanoid robots and physical AI edge platforms. This builds on Inova’s automotive expertise in zonal architectures to enable mixed-criticality compute featuring real-time control loops and secure AI workloads, and built on the same 22FDX process as SCI’s ICENI microcontroller.
Inova’s APXpress high-speed interface will be used with the MIPS Atlas M8500 RISC-V high-performance MCU IP, MIPS Atlas S8200 RISC-V AI processor IP and mixed signal to create a custom system on chip (SoC) for robotics workloads.
“Together with Inova, we’re delivering a Physical AI reference platform that simplifies robot design, reduces BOM cost, and gives builders an open, standards-based path to create whole product families with low latency and functionally safe connectivity,” said Sameer Wasson, CEO of MIPS.
“Robotics is moving rapidly and the leaders will scale quickly and cost-effectively. By pairing INOVA’s high-speed communication links with MIPS’ open RISC-V compute and mixed signal technologies, this scalable reference platform turns ‘sense-think-act-communicate’ into a Physical AI building block that lowers risk, lowers cost, and accelerates time to market.”
“Advanced humanoids demand secure, deterministic connectivity and a scalable control backbone. We’re giving robot makers a zonal, RISC-V-based blueprint that cuts complexity and cost to help scale humanoids and advanced robotics from prototype to production faster,” said Robert Isele, CEO at Inova. “The creation of a reference zonal architecture for advanced robotics will enable simpler and faster creation of humanoid and other robotic form factors.”
Early access to the platform is through the MIPS Atlas Explorer, a simulation-based hardware/software co-design platform. This gives software developers access to virtual representations of the compute elements and MCUs to start optimization of vision language action models preparing the foundational model for the robotics control reference architecture.
www.scisemi.com; www.ambientscientific.ai; www.siliconlabs.com; www.st.com; www.nordicsemi.com; inova-semiconductors.de/; www.globalfoundries.com;
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
